1. Advantages and disadvantages of Mealy and Moore?

2. What happens when the gate oxide is very thin?

3. Differences between netlist of HSPICE and Spectre?

4. 6-T XOR gate?

5. Define threshold voltage?

6. Explain Custom Design Flow?

7. What r the phenomenon which come into play when the devices are scaled to the sub-micron lengths?

8. Explain the concept of a Clock Divider Circuit? Write a VHDL code for the same?

9. For a single computer processor computer system, what is the purpose of a processor cache and describe its operation?

10. In what cases do you need to double clock a signal before presenting it to a synchronous state machine?

11. What work have you done on full chip Clock and Power distribution? What process technology and budgets were used?

12. If not into production, how far did you follow the design and why did not you see it into production?

13. Implement F= not (AB+CD) using CMOS gates?

14. Differences between D-Latch and D flip-flop?

15. Implement a 2 I/P and gate using Tran gates?

16. Id vs. Vds Characteristics of NMOS and PMOS transistors?

17. What is setup time and hold time?

18. What is FPGA?

19. Differences between blocking and Non-blocking statements in Verilog?

20. Factors affecting Power Consumption on a chip?

21. Why is Extraction performed?

22. What is clock feed through?

 23. Which gate is normally preferred while implementing circuits using CMOS logic, NAND or NOR? Why?

24. Explain the operation considering a two processor computer system with a cache for each processor.

25. You have a driver that drives a long signal & connects to an input device. At the input device there is either overshoot, undershoot or signal threshold violations, what can be done to correct this problem?

26. What types of I/O have you designed? What were their size? Speed? Configuration? Voltage requirements?